Many non-volatile memory devices, such as electrically erasable programmable read-only memories (EEPROMs), EPROMs, and FLASH EPROM memories, require relatively high voltage potentials for writing or erasing information, typically in the range of approximately 12-20 Volts. Because power supplies of contemporary digital systems supply a much lower voltage, for example 2-5 Volts, various methods of high-voltage generation have been used to "pump up", or increase, the power supply voltage Vcc to the potential required by non-volatile memories.
FIG. 1 illustrates a conventional charge pump circuit 10 used for high-voltage generation. The charge pump circuit 10, commonly referred to as "voltage multiplier," increases (or "pumps up") the amplitude of the power supply voltage Vcc to a programming/erase voltage Vpp required by non-volatile memories.
The charge pump circuit 10 comprises several pump stages 11, 12, 13, 14, and 15 connected in series. Pump stage 15 represents the nth pump stage. Each pump stage 11, 12, 13, 14, and 15 respectively comprises capacitors C1, C2, C3, C4, and Cn connected to respective gate terminals of diode-connected NMOS transistors MN2, MN3, MN4, MN5 and MNn. The power supply voltage Vcc is coupled through a diode-connected NMOS transistor MN1 to a source of transistor MN2 of the first pump stage 11. The pumped up output voltage Vout is received from a drain of the transistor MNn in the nth pump stage 15. Each of the pump stages 11, 12, 13, 14, and 15 is coupled to one of a pair of complementary clock signals P1 and P2 (refer to FIG. 2) through capacitors C1, C2, C3, C4, and Cn, respectively.
During operation, the capacitors C1, C2, C3, C4, and Cn are successively charged and discharged during each half of the clock signal. Specifically, capacitor C1 is charged through the diode-connected NMOS transistor MN1 as the clock signal P1 transitions to a low level, and capacitor C3 is charged via the current path through capacitor C2, the diode-connected NMOS transistor MN3 and positive-transitioning clock P2. Charge is transferred from capacitor C1 to capacitor C2 through the diode-connected NMOS transistor MN2 when the clock signals P1 and P2 reverse polarity. Charge transfer is constrained by transistors MN1 . . . MNn to be in a direction from left to right.
As capacitors C1, C2, C3, C4, and Cn are successively charged and discharged, packets of charge are "pumped" along the diode-connected NMOS transistors MN1 . . . MNn. The average voltage potential at the drains of the diode-connected NMOS transistors MN1 . . . MNn increases progressively from stage 11 to the output Vout of the diode-connected NMOS transistor chain. Thus, the voltage generated at the drain of the diode-connected NMOS transistor MNn at node Vout has a greater amplitude than the power supply voltage Vcc. When the power supply voltage is 5 Volts, the charge pump circuit 10 is sufficient for generating the high voltages required by non-volatile memories. In this scenario, for example, approximately 10 pump stages are utilized.
In the conventional embodiment, the bulk-to-source voltage Vsb increases as the power supply voltage Vcc is pumped up through the pump stages, causing respective threshold voltages Vts of the diode-connected NMOS transistors MN1 . . . MNn to be increased, as shown in FIG. 3, according to a phenomenon known as "body effect" (sometimes referred to as a substrate bias effect). The body effect causes the conductance of a transistor to decrease, that is, it increases the threshold voltages Vt of each transistor. As conduction of the transistors decreases, the upper pump stages, for example stage 15, become highly resistive, which severely limits current.
Thus, there is a need for a charge pump circuit capable of generating the high voltages required by non-volatile memories from a low power supply voltage without incrementally increasing threshold voltage.